Thermal management in semiconductor devices and circuits is a critical design element in any manufacturable and cost-effective electronic and optoelectronic product, such as light generation and electrical signal amplification. The goal of efficient thermal design is to lower the operating temperature of such electronic or optoelectronic devices while maximizing performance (power and speed) and reliability. Examples of such devices are microwave transistors, light-emitting diodes and lasers.
In recent years, devices and circuits based on gallium nitride (GaN) and other wide-gap semiconductors have surfaced as new choices for power amplifiers, visible-light generating optoelectronics, and power electronics. Unfortunately, heat extraction is a problem since GaN has relatively low thermal conductivity (lower than silicon). Integrating GaN with synthetic diamond substrates is a technology that promises to enable high-efficiency heat extraction from GaN devices. However, heat extraction and microwave performance and device cost are generally difficult to satisfy at once.
This application discloses device structures and methods for realizing high-performance RF and mm-wave GaN field-effect transistors on diamond integrated with carrier substrates which are then used to form thermally efficient packages with high-performance electrical interconnects.
Flip-chip technology refers to semiconductor die mounting technology in which the die is mounted upside-down with its front surface (where the transistors are located) to a substrate using electrical contacts that are prepared on both the front surface of the die and the top surface of the substrate on which the die is to be attached. The advantages of flip-chip technology over wire-bonding (used in most chip interconnect technologies) in microwave and milimeterwave applications are many: die mounting and electrical contacts are generally accomplished simultaneously, they yield smoother assembly process and better signal integrity (direct soldered connections typically have less inductance than wire bonds). Eliminating wire-bonds has several advantages: gold is used for wirebonds, and the wire-bond inductance is not as well controlled as solder bumps in flip-chip technology. This is particularly important for commercial work at mm-wave frequencies.
There are three main building blocks for flip-chip technology: the bumps on the chip preparation, the substrate, and the method of joining the chip to the substrate. There have been numerous development in the industry to apply this technology to high frequency applications. The process in which flip-chips are attached to substrates is called die-bonding and is usually performed with automated equipment. In order to assure good alignment, often a two-camera vision system is used to index the pads on the chip to the substrate. Alignment is critical to RF interconnect performance, but the best equipment of today can routinely align chips to better than five micrometers. For more information see references [8] and [9] incorporated here as a reference.
The electrical and optical activity in many electronic and optoelectronic semiconductor devices occurs at the surface of the chip, namely, the active current flows laterally close to the surface of the chip and the device terminals are proximal to the same side of the chip. Examples of such surface devices are field-effect transistors, microwave switch diodes, and light-emitting devices such as super luminescent diodes, semiconductor lasers, and light-emitting diodes.
Flip-chip technology is based on providing contacts to one plane of the chip and is hence optimal for realizing good signal integrity. Most microwave chips are designed in microstrip fashion in which the top surface contains the active signals and the chip backside the return path. The back is conventionally used to as ground. The connections from the front to the back are accomplished using vias.
However, flip-chip technology has one main disadvantage: heat removal. The substrate is the heatsink and the heat has to be extracted through the metal bumps. For power circuits, such as, amplifiers this is a critical problem. The improvement of heat extraction in high-power field-effect transistors, specifically, GaN transistors is based on optimizing heat extraction through the solder bumps see references [5], [6], [7], which are incorporated here as a reference.
FIG. 1 (PRIOR ART) shows two arrangements for assembling and die-attaching a field-effect transistor known in the art. The field-effect transistor 100 comprising a substrate 101, semiconductor epilayers 102 containing the field-effect transistor channel 103, metal contacts to the source 104, gate 105, and the drain 106 disposed on top of the epilayers 102. The chip 100 is attached to a heatsink 110 at the chip bottom surface 109. The semiconductor epilayers 102 feature a conductive channel 103 whose carrier density is modulated using the voltage on the gate 105. In a high-electron mobility transistor, the conductive channel 103 is a two-dimensional electron gas realized at the heterojunction interface between two semiconductors. In normal operation (linear or switch-mode operation), most of the heat is generated in the areas between the source and the drain (area shown with 107) and then is spread and conducted through the substrate 101 to the heatsink 110 across the chip bottom surface 109. The heat spreading and conduction is illustratively shown using arrows 108. Heat removal by conduction of heat through the substrate 101 to the bottom side of chip 109 is the most efficient heat extraction scheme. This is especially true when a highly thermally-conductive substrate is used. The disadvantage of the mounting arrangement illustrated in FIG. 1(a) is that bond-wires (not shown) have to be used to connect the metal contacts 104, 105, and 106 on the top surface of the chip 100 to the external circuitry (not shown). At high frequency, these bond-wires degrade the performance of the chip due to their parasitic inductance.
An alternative assembly configuration uses flip-chip technology and is illustrated in FIG. 1(b). Here a field-effect transistor 150, comprising of a substrate 151, epilayers 152, metal contacts 155, is connected to the heatsink 160 using solder bumps 154 to metal traces on the substrate 160 (not shown) as is well known in the art. The heat generated in area 157 is then conducted to the heatsink 160 via any number of solder-bumps 154 as indicated with the arrows 158. Very little heat is typically taken out of the back-side 159, especially if the substrate is made out of a low conductivity material. The disadvantage of the setup shown in FIG. 1(b) is that many solder bumps are necessary to conduct the heat away and yet there are areas between the chip 150 and the heatsink 160 with under-fill or glob-top that help the flip-chip assembly and reliability, but do not add to the thermal conductivity. Solder bumps can be as small as 25 um in diameter and 30 to 100 μm in height. The advantage of using flip chip is in the signal integrity and the simplicity in volume assembly.
Heat extraction from flip-chip mounted devices is commonly done through the solder-bumps, but also taking the heat from the top (surface 159 in FIG. 1(b)). This is not common in high-power devices as it involves heat-conductive adhesives and pastes that generally have poor heat conductivity relative to metals and some semiconductors. Another reason why taking the heat out of the top of the chip (surface 159) is uncommon and difficult is managing the tolerance stack-up between the chip package and the chip thickness in the presence of thermal expansion and manufacturing variations.
It is clear that industry has a need for a device and package technology that simultaneously delivers high signal integrity and low thermal resistance.